Some types of memory devices refresh the stored data periodically for preserving the information and improving storage reliability. Memory devices of certain technologies, such as Ferroelectric Random Access Memory (FeRAM or FRAM), may suffer from reliability degradation due to an imprint effect, in which the memory cells tend to prefer polarization states corresponding to data that has been stored in these cells for a long period of time.
Methods for mitigating imprint effects are known in the art. For example, U.S. Pat. No. 5,745,403, whose disclosure is incorporated herein by reference, describes a system and a method for mitigating undesired imprint effects in a ferroelectric memory array through the addition of a complementary data path which allows user data to be written to the array in an inverted state and then subsequently read out from the array in a reinverted state in response to the state of at least one indicator bit corresponding to each row of the array.
As another example, U.S. Pat. No. 8,495,438, whose disclosure is incorporated herein by reference, describes a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload or an inversion of the actual payload. The inversion condition bit and memory word are selectively toggled by a control circuitry. Inversion is performed by reading the inversion condition bit and memory word and rewriting the memory word back to the one or more memory cells in an inverted or non-inverted state, depending on an inversion condition bit. The inversion condition bit is then written to the inversion status bit value.